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International Journal

2017

  1. Tuy Tan Nguyen, Donghyun Kim, Van Huan Nguyen, Hanho Lee, and Hakil Kim, "A High-Security Fingerprint Authentication System using Ring-LWE Cryptography," IEEE Transactions on Information Forensics and Security, November 13, 2017. (submitted)
  2. Huyen Pham Thi, and Hanho Lee, "Basic-Set Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes with High-Order Galois-Fields," IEEE Transactions on VLSI Systems, June 26. 2017. (Accepted)
  3. Tuy Tan Nguyen and Hanho Lee, "High-Performance Ring-LWE Cryptography Scheme for Biometric Data Security," IET Information Security, April 10, 2017. (submitted)
  4. Sabooh Ajaz, Tram Thi Bao Nguyen, and Hanho Lee, "An Area-Efficient Half-Row Pipelined Layered LDPC Decoder Architecture," Journal of Semiconductor Technology and Science (JSTS), March 17, 2017. (Accepted)
  5. Huyen Pham Thi, Sabooh Ajaz and Hanho Lee, "High-Throughput Partial-Parallel Block-Layered Decoding Architecture for Nonbinary LDPC Codes," Integration, the VLSI Journal, vol. 59, pp. 52-63, Sept. 2017. [PDF]
  6. Huyen Pham Thi, and Hanho Lee, "Efficient Parallel Block-Layered Nonbinary LDPC Decoding on a GPU," IEIE Transactions on Smart Processing and Computing, vol. 6, no. 3, pp. 210-219, June 2017. [PDF]
  7. Huyen Pham Thi, and Hanho Lee, "Two-Extra-Column Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes" IEEE Transactions on VLSI Systems, Vol. 25, No. 5, pp. 1787-1791, May 2017. [PDF]
  8. Tram Thi Bao Nguyen and Hanho Lee, "High-Throughput Low-Complexity Mixed-Radix FFT Processor using a Dual-Path Shared Complex Constant Multiplier," Journal of Semiconductor Technology and Science (JSTS), Vol. 17, No. 1, pp. 101-109, Feb. 2017. [PDF]


2016

  1. Boseok Jeong, Taesung Kim, Hanho Lee, "Low-Complexity Non-Iterative Soft-Decision BCH Decoder Architecture for WBAN Applications," Journal of Semiconductor and Science Technology, Vol. 16, No. 4, pp. 488-496, Aug. 2016. [PDF]
  2. Tuy Tan Nguyen and Hanho Lee, "Efficient Algorithm and Architecture for Elliptic Curve Cryptographic Processor," Journal of Semiconductor Technology and Science (JSTS), Vol. 16, No. 1, pp. 118-125, Feb. 2016. [PDF]
  3. Ha-Ram Yun, and Hanho Lee, "Simplified merged processing element for successive-cancellation polar decoder," IET Electronics Letters, Vol. 52, No. 4, pp. 270-272, Feb. 18. 2016. [PDF]

2015

  1. Sabooh Ajaz, Hanho Lee, "Efficient multi-Gb/s multi-mode LDPC decoder architecture for IEEE 802.11ad applications," Integration, the VLSI Journal, vol.51, No. 3, pp. 21-36, Sept. 2015.[PDF]
  2. Cheolho Kim, Haram Yun, Sabooh Ajaz, Hanho Lee, "High-Throughput Low-Complexity Successive-Cancellation Polar Decoder Architecture", Journal of Semiconductor Technology and Science (JSTS), Vol.15, No. 3, pp. 427-435, Jun, 2015.[PDF]
  3. Chang-Seok Choi and Hanho Lee, “A Block-Layered Decoder Architecture for Quasi-Cyclic Non-Binary LDPC Codes,” Journal of Signal Processing Systems, Vol. 78, No. 2, pp. 209-222, Feb. 2015.[PDF]

2014

  1. Sabooh Ajaz and Hanho Lee, “An efficient radix-4 Quasi-cyclic shift network for QC-LDPC decoders," IEICE Electronics Express, vol. 11, No. 2, pp. 1-6, Jan. 25, 2014.[PDF]

2013

  1. Jaewoong Yeon, Seung-Jun Yang, Chelho Kim, Hanho Lee, “Low-Complexity Triple-Error-Correcting Parallel BCH Decoder,” Journal of Semiconductor and Science Technology, vol.13, no. 5, pp. 465-472, Oct. 2013.[PDF]
  2. Sabooh Ajaz and Hanho Lee, "Reduced-complexity local switch based multi-mode QC-LDPC decoder architecture for gigabit wireless communications," IET Electronics Letters, vol. 49, no. 19, pp. 1246-1248, Sept. 12. 2013. [PDF]
  3. Seong-In Hwang, Hanho Lee, “Block-Circulant RS-LDPC Code: Code Construction and Efficient Decoder Design,” IEEE Transactions on VLSI Systems, vol.21, no. 7, pp. 1337-1341, July 2013. [PDF]
  4. Taesang Cho and Hanho Lee, “A High-Speed Low-Complexity Modified Radix-2^5 FFT Processor for High-Rate WPAN Applications,” IEEE Transactions on VLSI Systems, Vol. 21, NO. 1, pp. 187-191, Jan 2013. [PDF]

2012

  1. Jeong-In Park, and Hanho Lee, “A High-Speed Low-Complexity Time-Multiplexing Reed-Solomon-Based FEC Architecture for Optical Communications,” IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences, Vol.E95-A, no. 12, pp. 2424-2429, Dec. 1. 2012. [PDF]
  2. Kihoon Lee, Han-Gil Kang, Jeong-In Park, Hanho Lee, “A High-Speed Low-Complexity Concatenated BCH Decoder Architecture for 100Gb/s Optical Communications,” Journal of Signal Processing Systems, vol. 6, no. 1, pp. 43-55, Jan. 2012. [PDF]


2011

  1. Kisun Jung, Hanho Lee, “Low-Complexity Multi-Mode Memory-based FFT Processor for DVB-T2 Applications,” IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences, Systems, vol.E94-A, no. 11, pp. 2376-2383, Nov. 2011. [PDF]
  2. Sangmin Kim, Gerald E. Sobelman, and Hanho Lee, "A Reduced-Complexity Architecture for LDPC Layered Decoding Schemes," IEEE Transactions on VLSI Systems, vol. 19, no. 6, pp. 1099-1103, June 2011 [PDF]
  3. Chang-Seok Choi, Hyo-Jin Ahn, Hanho Lee, "High-Throughput Low-Complexity Four-Parallel Reed-Solomon Decoder Architecture for High-Rate WPAN Systems," IEICE Transactions on Communications, Vol.E94-B,No.05,pp.1332-1338, May 2011. [PDF]
  4. Yong-Kyu Kim, Chang-Seok Choi, Hanho Lee, “Low-Complexity Filter Architecture for ATSC Terrestrial Broadcasting DTV Systems,” IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences, Systems Vol. E94-A, No. 3, pp. 937-945 , March 2011. [PDF]
  5. Jeong-In Park and Hanho Lee , "Area-Efficient Truncated Berlekamp-Massey Architecture for Reed-Solomon Decoders,” IET Electronics Letters,vol. 47, no. 4, pp. 241-243, Feb. 17, 2011.[PDF]

2010

  1. Jeong-In Park, Kihoon Lee, Chang-Seok Choi, Hanho Lee, “High-Speed Low-Complexity Reed-Solomon Decoder using Pipelined Berlekamp-Massey algorithm and Its Folded Architecture,” Journal of Semiconductor Technology and Science, vol. 10, no. 3, pp. 193 ~ 202, Sept. 2010. [PDF]
  2. Sangho Yoon, Hanho Lee, Kihoon Lee, "High-Speed Two-Parallel Concatenated BCH-based Super-FEC Architecture for Optical Communications," IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences, Systems, vol. E92-A, No. 4, pp.769-777, April, 2010. [PDF]

1998 ~ 2008

  1. T-S. Kim, Hanho Lee, J. Park, C-H. Lee, Y-M. Lee, C-S. Choi, S-G. Hwang, H. D. Kim, C. H. Min, "Ubiquitous Evolvable Hardware System for Heart Diseases Diagnosis Applications," International Journal of Electronics, vol. 95, no. 7, pp. 637-651, July 2008. (SCI) [PDF]
  2. Seungbeom Lee, Chang-Seok Choi, and Hanho Lee, "Two-parallel Reed-Solomon based FEC architecture for optical communications," IEICE Electronics Express (ELEX), vol. 5, no. 10, pp. 374-380, May 1. 2008. (SCIE) [PDF]
  3. Jeesung Lee and Hanho Lee, "A High-Speed 2-Parallel Radix-2^4 FFT/IFFT Processor for MB-OFDM UWB Systems," IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences, vol. E91-A, no. 4, pp. 1206-1211, April 2008. (SCIE) [PDF]
  4. Seungbeom Lee and Hanho Lee, "A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders," IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences . vol. E91-A, no. 3, pp. 830-835, March 2008. (SCIE) [PDF]
  5. Chang-Seok Choi and Hanho Lee, "A Self- Reconfigurable Adaptive FIR Filter System on Partial Reconfiguration Platform," IEICE Transactions on Information and Systems, vol. E90-D, no. 12, pp. 1932-1938, Dec. 1. 2007. (SCIE) [PDF]
  6. Cheol-Ho Shin, Sangsung Choi, Hanho Lee, Jeong-Ki Pack, "A Design and Performance of 4-Parallel MB-OFDM UWB Receiver," IEICE Transactions on Communications, vol.E90-B, no. 3, pp. 672-675, March 2007. (SCI) [PDF]
  7. Hanho Lee, Chang-Seok Choi, "Implementation of a FIR Filter on a Partial Reconfigurable Platform," KES2006, LNAI4253, Part III, pp. 108-115, Oct. 2006. (SCIE) [PDF]
  8. Yeong-Jae Oh, Hanho Lee, Chong-Ho Lee, "Dynamic Partial Reconfigurable FIR Filter Design," Reconfigurbale Computing: Architectures and Applications (ARC 2006), LNCS3985, Mar. 2006. (SCIE) [PDF]
  9. Hanho Lee, "Power-Aware Scalable Booth Multiplier," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E88-A, No. 11, pp.3230-3234, Nov. 2005. (SCIE) [PDF]
  10. Hanho Lee, "Reconfigurable Power-Aware Scalable Booth Multiplier," KES2005, LNAI, Part I, pp. 176-183, Sept. 2005. (SCIE) [PDF]
  11. I. J. Jeon, P. K. Rhee, Hanho Lee, " An Evolvable Hardware System under Uneven Environment," KES2005, LNAI, Part II, pp. 319-326, Sept. 2005.(SCIE) [PDF]
  12. Hanho Lee, " A High-Speed, Low-Complexity Reed-Solomon Decoder for Optical Communications ," IEEE Transactions on Circuits and Systems-II, vol. 52, No. 8, pp. 461-465, Aug. 2005. (SCI) [PDF]
  13. Hanho Lee and G. E. Sobelman, VLSI Design of Digit-Serial FPGA Architecture, Journal of Circuits, Systems, and Computers , Vol. 13, No. 1, pp. 17-52, Feb. 2004. (SCIE) [PDF]
  14. Hanho Lee and Asad Azam Pipelined Recursive Modified Euclidean Algorithm Block for Low-Complexity, High-Speed Reed-Solomon Decoder , IEE Electronics Letters , Vol. 39, No. 19, pp. 1371-1372, Sept 17. 2003. (SCI) [PDF]
  15. Hanho Lee, High-Speed VLSI Architecture for Parallel Reed-Solomon Decoder , IEEE Transactions on VLSI Systems , Vol. 11, No. 2, pp. 288-294, April 2003. [PDF]
  16. Hanho Lee and G. E. Sobelman, "Performance Evaluation and Optimal Design for FPGA-Based Digit-Serial DSP Functions, An International Journal Computers & Electrical Engineering , Vol. 29, No. 2, pp. 357-377, March 2003.
  17. Hanho Lee and G. E. Sobelman, "FPGA-Based Digit-Serial CSD FIR Filter for Image Signal Format Conversion, Microelectronics Journal , Vol. 33, pp. 501-508, April 2002.
  18. Hanho Lee, Modified Euclidean Algorithm Block for High-Speed Reed-Solomon Decoder , IEE Electronics Letters , pp. 903-904, Vol. 37, No. 14, July 2001. [PDF]
  19. Hanho Lee and G. E. Sobelman, "A Comparative Study of Glitch-free TSPC D flip-flop Circuits at a Low Supply Voltage, Microelectronics Journal , Vol.29, No.12, pp. 1025-1031, Dec. 1998.
  20. Hanho Lee and G. E. Sobelman, "New XOR/XNOR and Full Adder Circuits for Low-Voltage, Low-Power Applications, Microelectonics Journal , Vol. 29, No.8, pp. 509-517, Aug. 1998.


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